The present invention relates to a semiconductor device, and more particularly, to a semiconductor device incorporating a rail-to-rail amplifier (differential amplifier) used as an interface circuit complying with IEEE 1394.b.
In an interface circuit complying with IEEE 1394.b, if the input voltage range is 0 to 3.0 V, for example, it is determined that a signal does not exist when an input signal has an amplitude of less than 80 mV, and determined that a signal exists when an input signal has an amplitude of 200 mV or greater. To satisfy such a specification, a rail-to-rail amplifier is used in an input stage circuit of an interface circuit. The rail-to-rail amplifier includes a differential pair operated when an input signal has a relatively high potential in an input voltage range and a further differential pair operated when an input signal has a low potential in the input voltage range. Thus, the rail-to-rail amplifier functions stably when an input voltage fluctuates between a high potential power supply and a low potential power supply.
FIG. 1 is a circuit diagram showing a prior art rail-to-rail amplifier (amp) 100. An input differential pair is configured by n-channel MOS transistors Tr1 and Tr2. An input signal Vin1 is provided to the gate of the transistor Tr1, and an input signal Vin2 is provided to the gate of the transistor Tr2.
Further, an input differential pair is configured by p-channel MOS transistors Tr3 and Tr4. The input signal Vin2 is provided to the gate of the transistor Tr3, and the input signal Vin1 is provided to the gate of the transistor Tr4. Referring to FIG. 3A, the input signals Vin1 and Vin2 are complementary signals having amplitudes of about, for example, 80 mV.
The sources of the transistors Tr3 and Tr4 are connected to a current source 1, which is further connected to a power supply VDD. Accordingly, operation currents Ip1 and Ip2 corresponding to the input signals Vin2 and Vin1 flow through the transistors Tr3 and Tr4, respectively.
The sources of the transistors Tr1 and Tr2 are connected to a current source 2, which is further connected to a power supply Vss. The drain of the transistor Tr1 is connected to the drain and gate of a p-channel MOS transistor Tr5. The source of the transistor Tr5 is connected to the power supply VDD. The drain of the transistor Tr2 is connected to the drain and gate of a p-channel MOS transistor Tr6. The source of the transistor Tr6 is connected to the power supply VDD. Accordingly, operation currents In1 and In2 corresponding to the input signals Vin1 and Vin2 flow through the transistors Tr1 and Tr2, respectively.
The gate of the transistor Tr5 is connected to the gate of a p-channel MOS transistor Tr7. The source of the transistor Tr7 is connected to the power supply VDD. The drain of the transistor Tr7 is connected to the drain and gate of an n-channel MOS transistor Tr9. The drain of the transistor Tr9 is connected to the drain of the transistor Tr3. The source of the transistor Tr9 is connected to the power supply Vss.
The gate of the transistor Tr6 is connected to the gate of a p-channel MOS transistor Tr8. The source of the transistor Tr8 is connected to the power supply VDD. The drain of the transistor Tr8 is connected to the drain and gate of an n-channel MOS transistor Tr10. The drain of the transistor Tr10 is connected to the drain of the transistor Tr4. The source of the transistor Tr10 is connected to the power supply Vss.
Accordingly, the transistors Tr5 and Tr7 and the transistors Tr6 and Tr8 perform a current mirror operation. The drain current of the transistor Tr7 flows through the transistor Tr9, and the drain current of the transistor Tr8 flows through the transistor Tr10.
Referring to FIG. 2, in the rail-to-rail amp 100, when the center voltage of the input signals Vin1 and Vin2 is near the power supply VDD, the input differential pair configured mainly by the n-channel MOS transistors, or the transistors Tr1 and Tr2, is operated. Current corresponding to the operation currents In1 and In2 associated with the transistors Tr1 and Tr2 flow through the transistors Tr9 and Tr10 as output currents Io1 and Io2, respectively.
When the center voltage of the input signals Vin1 and Vin2 is near the power supply Vss, the input differential pair configured mainly by the p-channel MOS transistors, or the transistors Tr3 and Tr4, is operated. Current corresponding to the operation currents Ip1 and Ip2 associated with the transistors Tr3 and Tr4 flow through the transistors Tr9 and Tr10 as the output currents Io1 and Io2, respectively.
For example, based on the size of the transistors Tr9 and Tr10 and the size of other transistors, the amplification rate may be set to “2”. In such a case, when the rail-to-rail amp 100 is supplied with the input signals Vin1 and Vin2 having amplitudes of 80 mV as shown in FIG. 3A, output signals Vout1 and Vout 2 having amplitudes of 160 mV are output from the drains of the transistors Tr9 and Tr10, respectively. In this manner, the transistors Tr5 and Tr7 (current mirror circuit), the transistors Tr6 and Tr8 (current mirror circuit), and the transistors Tr9 and Tr10 synthesize the operation current of each input differential pair and function as a current synthesizing circuit that generates the output voltages Vout1 and Vout2.
As the center voltage of the input signals Vin1 and Vin2 approaches an intermediate level between the power supply VDD and the power supply Vss, the transistors Tr1 and Tr2 in addition to the transistors Tr3 and Tr4 are operated. Thus, the output currents Io1 and Io2 flowing through the transistors Tr9 and Tr10 increase. When the center voltage of the input signals Vin1 and Vin2 reach the intermediate level between the power supply VDD and the power supply Vss, the transistors Tr1 and TR2 and the transistors Tr3 and Tr4 are operated in a substantially saturated state. Thus, referring to FIG. 2, the maximum output currents Io1 and Io2 flow through the transistors Tr9 and Tr10. In this case, the amplitudes of the output voltages increases to 320 mV, as shown in FIG. 3C, even though the amplitudes of the input signals Vin1 and Vin2 is 80 mV.
In this manner, the amplification rate of the rail-to-rail amp 100 increases when the center voltage of the input signals Vin1 and Vin2 is near the intermediate level between the power supply VDD and the power supply Vss. Accordingly, in this case, even if the amplitudes of the input signals Vin1 and Vin2 are less than 80 mV, due to the increase in the amplitudes of the output voltages Vout1 and Vout2, the circuit in the following stage may determine that a signal exists based on the output voltages Vout1 and Vout2 respectively corresponding to the input signals Vin1 and Vin2, which are less than 80 mV.
FIG. 4 is a circuit diagram of an input stage circuit 200 which includes a means for suppressing output voltage fluctuation with respect to fluctuations of the center voltage of the input signals Vin1 and Vin2. In the input stage circuit 200, n-channel MOS transistors Tr11 and Tr12 configure an input differential pair, and p-channel MOS transistors Tr13 and Tr14 configure a further input differential pair. The transistors Tr11 and Tr12 are supplied with operation current from a current source 3. The transistors Tr13 and Tr14 are supplied with operation current from a current source 4.
Transistors Tr15 to Tr18 and resistors R1 to R4 configure an output circuit that synthesizes the operation currents of the input differential pairs and generate an output voltage Vout. The input stage circuit 200 further includes a tail current controller provided with an n-channel MOS transistor Tr19 and a p-channel MOS transistor Tr20, each of which functions as a current switch, constant voltage sources 5 and 6, and current mirror circuits 7 and 8. The tail current controller suppresses fluctuation of the output voltage Vout relative to fluctuations in the power supply voltage of the input signals Vin1 and Vin2.
The transistor Tr20 is activated and the current mirror circuit 8 is operated when the center voltage of the input signals Vin1 and Vin2 reaches a level close to the power supply VDD. The size of n-channel MOS transistors Tr21 and Tr22, which configure the current mirror circuit 8, is set at 1:3. Thus, current that is three times greater than the drain current flowing through the transistor Tr21 flows through the transistor Tr22, or the transistors Tr11 and Tr12.
The transistor Tr19 is activated and the current mirror 7 is operated when the center voltage of the input signals Vin1 and Vin2 reaches a level close to the power supply Vss. The size of p-channel MOS transistors Tr23 and Tr24, which configure the current mirror circuit 7, is set at 1:3. Thus, current that is three times greater than the drain current flowing through the transistor Tr23 flows through the transistor Tr24, or the transistors Tr13 and Tr14. Such operation levels the operation current flowing through the transistors Tr11 to Tr14 with respect to fluctuations in the center voltage of the input signals Vin1 and Vin2. This suppresses fluctuation of the output voltage Vout.
Japanese Laid-Open Patent Publication No. 2002-43871 describes a rail-to-rail amp that prevents deficient operations resulting from fluctuations in the input signal and that suppresses fluctuation of the output voltage relative to fluctuations in the center voltage of the input signal if there is no potential difference between input signals provided to a differential pair.